Description
Revision Standard – Superseded.The definition of the language syntax and semantics for SystemVerilog, which is a unifiedhardware design, specification, and verification language, is provided. This standard includessupport for modeling hardware at the behavioral, register transfer level (RTL), and gate-levelabstraction levels, and for writing test benches using coverage, assertions, object-orientedprogramming, and constrained random verification. The standard also provides applicationprogramming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)
Product Details
- Published:
- 02/21/2013
- ISBN(s):
- 9780738181103
- Number of Pages:
- 1312
- File Size:
- 1 file , 6.7 MB
- Product Code(s):
- STDSU98078
- Note:
- This product is unavailable in Russia, Belarus
